A typical transistor has a source/drain region, which is defined by forming an impurity diffusion layer at a semiconductor substrate. A PN junction is formed between the source/drain region and the semiconductor substrate. Accordingly, the semiconductor substrate and the source/drain region are electrically isolated from each other when a reverse bias is applied therebetween.
With trends toward higher integration of semiconductor devices, a depth of the source/drain region is continually reduced. For this reason, current leakage, current leaked into the semiconductor substrate through the source/drain region, can become a serious problem. One proposed solution to suppress the current leakage is by placing a silicon-on-insulator layer on the substrate (hereinafter referred to as an “SOI substrate”). The SOI substrate has a structure where a buried oxide layer is disposed apart from a surface of the semiconductor substrate at a predetermined depth. The buried oxide layer may serve to prevent the leakage current through the source/drain region. However, in the case that the impurities used to form the source/drain region are boron ions, the boron ions can be diffused into the buried oxide layer.
FIG. 1 is a cross-sectional view showing a transistor formed at an SOI semiconductor substrate and FIG. 2 is a graph showing an impurity density, taken along a line I–I′ of FIG. 1. As illustrated in FIG. 2, a horizontal axis represents a depth of a semiconductor substrate from a surface of an SOI layer and a vertical axis represents the impurity concentration according to the depth of the semiconductor substrate.
Referring to FIGS. 1 and 2, buried oxide and SOI layers 2 and 3 are sequentially staked on an entire surface of a semiconductor substrate 1. A gate pattern 6 is disposed on an active region of the SOI layer 3 to cross over the active region. The gate pattern 6 consists of a gate insulating layer 4 and a gate electrode 5, which are sequentially stacked on the active region. An impurity diffusion layer 7 is disposed at both active regions of the gate pattern 6. The impurity diffusion layer 7 corresponds to a source/drain region and is doped with boron ions. Thus, a transistor having the foregoing structure is to be a positive-channel metal oxide semiconductor (“PMOS”) transistor.
A line ‘A’ of FIG. 2 represents the boron ions concentration according to the depth of the semiconductor substrate. As shown by line ‘A’, the solubility and diffusion coefficient of the buried oxide layer 2 allows boron ions to be diffused into the buried oxide layer 2. Further, the boron ions may be diffused into the semiconductor substrate 1 through the buried oxide layer 2. Therefore, resistance of the impurity diffusion layer 7 is increased, thereby deteriorating characteristics of the transistor.
Also, in the case that the transistor is a negative-channel metal oxide semiconductor (“NMOS”) transistor (not shown), the boron ions are implanted into a channel region between the source and drain regions to control a threshold voltage. In this case, the boron ions may be diffused into the buried oxide layer 2 or the semiconductor substrate 1. Thus, the concentration of the implanted boron ions is reduced to vary the threshold voltage of the NMOS transistor.